Exemplary embodiments of the present invention relate to semiconductor design technology, and more particularly, to a semiconductor memory device for performing a data write operation on a memory bank using an input driver and a write driver.
In general, as the processing technology of a semiconductor memory device such as a double data rate synchronous dynamic random access memory device (DDR SDRAM) is highly developed, the number of memory banks employed in the semiconductor memory device is gradually increasing. Thus, the design technology of the semiconductor memory device is being diversified to effectively input/output a plurality of data stored in the memory banks. Among different types of the technology, there is a scheme of disposing the plurality of memory banks with a stack structure, and a data width option for establishing an interface between a controller and the semiconductor memory device as x4, x8, or x16.
For reference, the data width option enhances the variety of the interface of the semiconductor memory device and refers to an option capable of establishing a data width between the controller and the semiconductor memory device. For instance, in a semiconductor memory device employing 16 numbers of input/output pads, it is possible to establish the data width option as x16 or x8. In the case of establishing the data width option as x16, the semiconductor memory device performs a data transmission operation through the 16 numbers of input/output pads. Meanwhile, in the case of establishing the data width option as x8, the semiconductor memory device performs the data transmission operation through 8 numbers of input/output pads among the 16 numbers of input/output pads.
FIG. 1 illustrates a block diagram of a part of a conventional semiconductor memory device. For instance, the conventional semiconductor memory device employs 16 numbers of input/output pads (not shown) and has a structure capable of accomplishing the x8 or x16 data width option.
FIG. 1 shows first and second memory banks 110_1 and 130_2 each of which includes first and second sub-memory banks. That is, the first memory bank 110_1 includes first and second sub-memory banks 110_1L and 110_1R and the second memory bank 130_2 includes first and second sub-memory banks 130_2L and 130_2R. In the first and second sub-memory banks 110_1L, 110_1R, 130_2L, and 130_2R corresponding to the first and second memory banks 110_1 and 130_2, respectively, a write operation is performed by their corresponding write driving blocks and input driving blocks.
Namely, in the first sub-memory bank 110_1L corresponding to the first memory bank 110_1, the write operation is performed by a write driving block 150_1L and an input driving block 170_1L. In the second sub-memory bank 110_1R corresponding to the first memory bank 110_1, the write operation is performed by a write driving block 150_1R and an input driving block 170_1R. In the first sub-memory bank 130_2L corresponding to the second memory bank 130_2, the write operation is performed by a write driving block 150_2L and an input driving block 170_2L. In the second sub-memory bank 130_2R corresponding to the second memory bank 130_2, the write operation is performed by a write driving block 150_2R and an input driving block 170_2R.
The input driving blocks 170_11, 170_2L, 170_1R, and 170_2R are respectively under the control of input control signals CTR_1L, CTR_2L, CTR_1R, and CTR_2R, and transmit data transferred through corresponding global input/output lines GIO_U and GIO_D to the write driving blocks 150_1L, 150_2L, 150_1R, and 150_2R, respectively. Herein, the global input/output lines GIO_U and GIO_D may be divided into the up global input/output line GIO_U and the down global input/output line GIO_D. Each of the up and down global input/output lines GIO_U and GIO_D corresponds to 8 input/output pads (not shown). The input driving blocks 170_1L, 170_2L, 170_1R, and 170_2R respectively receive the data transferred through the up global input/output line GIO_U and the down global input/output line GIO_D in response to the input control signals CTR_1L, CTR_2L, CTR_1R, and CTR_2R whose logic levels are determined according to the data width option. That is, the input control signals CTR_1L, CTR_2L, CTR_1R, and CTR_2R control the data transmitted through the up global input/output line GIO_U and the down global input/output line GIO_D to be inputted to the corresponding input driving blocks 170_1L, 170_2L, 170_1R, and 170_2R, respectively.
In the meantime, data outputted through each of the input driving blocks 170_1L, 170_2L, 170_1R, and 170_2R are inputted to a corresponding one of the write driving blocks 150_1L, 150_2L, 150_1R, and 150_2R. The write driving blocks 150_1L, 150_2L, 150_1R, and 150_2R perform a write operation on the first and second memory banks 110_1 and 130_2 for the data outputted from the input driving blocks 170_1L, 170_2L, 170_1R, and 170_2R in response to corresponding write activation signals BWEN_1L, BWEN_2L, BWEN_1R, and BWEN_2R, respectively.
FIG. 2 illustrates an activation signal generating block for generating the write activation signals BWEN_1L, BWEN_1R, BWEN_2L, and BWEN_2R described in FIG. 1.
Referring to FIG. 2, the activation signal generating block includes a logic combining sector 210 and a delay sector 230.
The logic combining sector 210 logically combines first and second bank strobe signals STB_BK1 and STB_BK2 and the input control signals CTR_1R, CTR_1L, CTR_2R, and CTR_2L. The delay sector 230 outputs the write activation signals BWEN_1R, BWEN_1L, BWEN_2R, and BWEN_2L by reflecting delay times corresponding to output signals of the logic combining sector 210. Herein, the first and second bank strobe signals STB_BK1 and STB_BK2 have information for a memory bank where access is performed of the first and second memory banks 110_1 and 130_2 described in FIG. 1. Therefore, the write activation signals BWEN_1R, BWEN_1L, BWEN_2R, and BWEN_2L, generated by logically combining the input control signals CTR_1R, CTR_1L, CTR_2R, and CTR_2L and the first and second bank strobe signals STB_BK1 and STB_BK2, have information for a memory bank where access is performed of the first and second memory banks 110_1 and 130_2, and information for the first and second sub-memory banks where the data write operation is performed.
FIG. 3 illustrates a timing diagram for explaining a circuit operation of the semiconductor memory device described in FIG. 1. Where the data width option is established as x8, the data are transmitted through the up global input/output line GIO_U and the transmitted data may be written in one of the first and second sub-memory banks 110_1L, 110_1R, 130_2L, and 130_2R of the first and second memory banks 110_1 and 130_2 according to a control scheme. For the simplicity of explanation, the following describes only the write operation in which the data transmitted through the up global input/output line GIO_U are written in the second sub-memory bank 110_1R of the first memory bank 110_1 in response to a first write command WT1, and the data transmitted through the up global input/output line GIO_U are written in the first sub-memory bank 130_2L of the second memory bank 130_2 in response to a second write command WT2.
Referring to FIGS. 1 to 3, in a state where the data width option is established as x8, the input control signals CTR_1R and CTR_2L have a logic high level to write the data transmitted through the up global input/output line GIO_U in the second sub-memory bank 110_1R of the first memory bank 110_1 and the first sub-memory bank 130_2L of the second memory bank 130_2, respectively.
First, if the first write command WT1 is inputted, the first bank strobe signal STB_BK1 corresponding to the first memory bank 110_1 is enabled and the data transmitted through the up global input/output line GIO_U are transferred to the write driving blocks 150_2L and 150_1R through the input driving blocks 170_2L and 170_1R, respectively. At this time, since only the write activation signal BWEN_1R is enabled, only the write driving block 150_1R is activated, and the data are written in the second sub-memory bank 110_1R of the first memory bank 110_1.
Then, if the second write command WT2 is inputted, the second bank strobe signal STB_BK2 corresponding to the second memory bank 130_2 is enabled and the data transmitted through the up global input/output line GIO_U are transferred to the write driving block 150_2L through the input driving block 170_2L, and written in the first sub-memory bank 130_2L of the second memory bank 130_2.
In the above description, the input control signals CTR_1L and CTR_2R have a logic low level, so as to reduce unnecessary power consumption during the write operation performed by the first and second write commands WT1 and WT2.
For reference, signals for controlling the data width option (not shown) are additionally inputted to the input driving blocks 170_1L, 170_2L, 170_1R, and 170_2R, and therefore, it is possible to perform a x16 data width option operation.
The conventional semiconductor memory device includes the input driving blocks 170_1L, 170_2L, 170_1R, and 170_2R to perform the data width option operation. Besides, it is required to include data lines to transmit the data outputted from the input driving blocks 170_1L, 170_2L, 170_1R, and 170_2R and control signal lines to transmit the input control signals CTR_1L, CTR_2L, CTR_1R, and CTR_2R for controlling the input driving blocks 170_1L, 170_2L, 170_1R, and 170_2R, respectively.
Recently, since the number of memory banks included in the semiconductor memory device is on an increasing trend, the semiconductor memory device adopts the stack structure as described in FIG. 1. As a result, the number of the input driving blocks 170_1L, 170_2L, 170_1R, and 170_2R further increases, and thus, the number of input/output data lines and the number of control signal lines corresponding to the input driving blocks 170_1L, 170_2L, 170_1R, and 170_2R also increase. The increase of the number of the input driving blocks 170_1L, 170_2L, 170_1R, and 170_2R causes the increase of an area occupied by the input driving blocks.
Moreover, because output data lines of input driving blocks 170_1L, 170_2L, 170_1R, and 170_2R are disposed to cross the memory banks, where the number of the output data lines increases, the increase acts as a big burden in designing the memory banks. Further, in case the number of the control signal lines corresponding to the input driving blocks 170_1L, 170_2L, 170_1R, and 170_2R also increases, the increased number also acts as a big burden in the circuit design.
Next, consider that the up global input/output line GIO_U is connected to the input driving blocks 170_1L, 170_2L, 170_1R, and 170_2R. Therefore, an increase in the number of input driving blocks may cause a problem in that a large load is put on the up global input/output line GIO_U.